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[VHDL-FPGA-Verilog] FPGA_SDRAM

Description: FPGA对SDRAM的控制操作源码,用VERILOG硬件描述语言编写,包含的文件一共有:hostcont.v,inc.h,pinouts.ucf,sdram.v,top.v,tst_inc.h-Control of operation of the SDRAM FPGA source code, using VERILOG hardware description language, the file contains a total of: hostcont.v, inc.h, pinouts.ucf, sdram.v, top.v, tst_inc.h
Platform: | Size: 21504 | Author: 陈维 | Hits:

[VHDL-FPGA-Verilog] paper_FPGA

Description: 基于FPGA控制的高速固态存储器设计，对固态存储器进行了需求分析, 根据航天工程对高速固态存储器的需求, 确定了设计方案。 针对航天工程对高速固态存储器速率要求较高的特点, 在逻辑设计方面采用流水线技术、并行总线技术。在器件选择方面, 采用LVDS构成接口电路, FPGA构成控制逻辑电路电路, SDRAM芯片阵列构成存储电路。设计了高速固态存储器。该设计简化了硬件电路, 大大提高了存储数据的速率。-FPGA-based control design of high speed solid state memory, solid state memory of the needs analysis carried out, according to aerospace engineering demand for high-speed solid-state memory, set design. Aerospace engineering for high-speed solid-state memory features require a higher rate, in the logic design using pipelining, parallel bus technology. In the device selection, the use of LVDS interface circuit composition, FPGA control logic circuit form, SDRAM chips constitute a memory circuit array. Design of high speed solid state memory. The design simplifies the hardware circuit, greatly increased the rate of stored data.
Platform: | Size: 262144 | Author: lyh | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s internal logic to realize the ADC, SDRAM, LAN controller chip DM9000 timing control to capture FPGA as the core of the system, through the ADC, will be collected The data stored in SDRAM, the SDRAM in order to read data from the FIFO method, and data results to a computer via Ethernet interface
Platform: | Size: 388096 | Author: gdr | Hits:

[Other] yadmc_latest.tar

Description: 基于wishbone总线的sdram控制器-sdram control with wishbone interface
Platform: | Size: 21504 | Author: yangjingjing | Hits:

[VHDL-FPGA-Verilog] SDRAM_MT198

Description: VERILGO SDRAM CONTROL
Platform: | Size: 8192 | Author: MCL | Hits:

[Software Engineering] HOW_TO_USE_SDRAM

Description: HOW TO USE SDRAM？尔必达的技术文档，详细阐述了SDRAM内存的控制原理，绝对值得研读和收藏！-HOW TO USE SDRAM? Elpida technical documentation described in detail SDRAM memory, control theory, definitely worth reading and collecting!
Platform: | Size: 344064 | Author: 方伟 | Hits:

[VHDL-FPGA-Verilog] SDRAMTEST

Description: SDRAM控制程序，可以作为一个IP核使用， 比自带的功能要多 可以稳定运行-SDRAM control procedures can be used as an IP core, more than the built-in capabilities can be stabilized to run
Platform: | Size: 8221696 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] sdram_mdl

Description: verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
Platform: | Size: 2286592 | Author: luoqv | Hits:

[VHDL-FPGA-Verilog] source

Description: SDRAM 控制, 用於SDRAM上 的代碼-SDRAM Control
Platform: | Size: 440320 | Author: wisdom | Hits:

[VHDL-FPGA-Verilog] UART_DMA

Description: 实用串口与SDRAM控制接口VHDL语言程序代码-Utility serial port and SDRAM control interface VHDL language code
Platform: | Size: 1009664 | Author: junlee | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM

Description: 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to achieve use of technology to achieve direct data acquisition, and automatic calibration circuit to adjust the data in line delay.
Platform: | Size: 54272 | Author: syf | Hits:

[VHDL-FPGA-Verilog] ddr_sdr

Description: DDR SDRAM 控制器 包含测试向量和仿真模型-DDR SDRAM control
Platform: | Size: 115712 | Author: 李晓翔 | Hits:

[VHDL-FPGA-Verilog] project1_supplemental1

Description: these are projects based on verilog like memory control, sdram control etc-these are projects based on verilog like memory control, sdram control etc..
Platform: | Size: 1764352 | Author: neeraj | Hits:

[Other Embeded program] SDRAM-Modelsim

Description: SDRAM读写控制的实现与Modelsim仿真-SDRAM read and write control to achieve with Modelsim Simulation
Platform: | Size: 2179072 | Author: 小明 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: sdram的学习使用控制源代码 有需要的同学可以下载-sdram learning to use the control source code can be downloaded to needy students
Platform: | Size: 58368 | Author: 安圣基 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: SDRAM 的读写，在仿真版上测试过的 可以用，源码+控制逻辑-SDRAM read and write, tested in the simulation version Can use the source code+ control logic
Platform: | Size: 2427904 | Author: ihyni | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 在ISE环境下对SDRAM(异步动态存储器)的控制模块设计。-In the ISE environment of SDRAM ( asynchronous DRAM ) control module design.
Platform: | Size: 12853248 | Author: 陈拓 | Hits:

[VHDL-FPGA-Verilog] vhdl_sdram

Description: Altera Sdram vhdl 控制代码-Altera Sdram vhdl control code
Platform: | Size: 11264 | Author: zhanshen | Hits:

[VHDL-FPGA-Verilog] sdr_sdram

Description: 用FPGA实现SDRAM的控制，主要是将SDRAM的时序搞懂，这个很好做出来了。-Using FPGA realize SDRAM control, mainly the SDRAM timing out, this is very good do.
Platform: | Size: 2570240 | Author: hanbo | Hits:

[VHDL-FPGA-Verilog] sdram

Description: SDram的读写控制。站长我是一名初学者，而且对其很感兴趣，但作为一个初学者起始是万般艰难的，我就只有这一源代码，奉上。望转正！万分谢谢。-The control SDram, reading and writing
Platform: | Size: 8192 | Author: 王建 | Hits:
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